1. Field of the Invention
This invention relates to FIFO circuits, and more particularly to low latency FIFO designs that interface subsystems working at different speeds and that may be synchronous or asynchronous, and between subsystems with very long interconnection delays.
2. Background of Related Art
A trend in VLSI is increasingly towards a “system-on-a-chip” involving many clock domains. A challenging problem is to robustly interface these domains. There have been few adequate solutions, especially ones providing reliable low-latency communication.
There are two fundamental challenges in designing systems-on-a-chip. A first challenge concerns systems operating under different timing assumptions. These timing assumptions include different clock speeds, as well as both synchronous and asynchronous environments. A second challenge concerns designs having long delays in communication between systems.
A number of FIFO circuits and components have been developed to handle timing discrepancies between subsystems. Some designs are limited to handling single-clock systems. These approaches have been proposed to handle clock skew, drift and jitter (R. Kol et al., “Adaptive Synchronization for Multi-Synchronous System,” IEEE International Conference on Computer Design (ICCD'98), pp. 188-189, October 1998; and M. Greenstreet, “Implementing a STARI Chip,” Proceedings IEEE International Conference on Computer Design (ICCD), pp. 38-43, 1995). To handle long interconnect delays, “latency—insensitive protocols” have been proposed (See, e.g., relay stations as disclosed in L. Carloni et al., “A Methodology for Correct-by-Construction Latency Insensitive Design,” ICCAD, 1999, which is incorporated by reference in its entirety herein); however their solution was limited to a single clock domain.
Several designs have also been proposed to handle mixed-timing domains. One category of design approaches attempts to synchronize data items and/or control signals with the receiver, without interfering with its clock. In particular, Seizovic robustly interfaces asynchronous with synchronous environments through a “synchronization FIFO”. (J. Seizovic, “Pipeline Synchronization,” Proceedings International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 87-96, November 1994). However, the latency of this design is proportional with the number of FIFO stages, whose implementation include expensive synchronizers. Furthermore, his design requires the sender to produce data items at a constant rate.
Other designs achieve robust interfacing of mixed-clock systems by temporarily modifying the receiver's clock. Synchronization failures are avoided by pausing or stretching the receiver's local clock. Each communicating synchronous system is wrapped with asynchronous logic, which is responsible for communicating with the other systems and for adjusting the clocks. This approach changes the local systems' clocks, and may introduce latency penalties in restarting them.
Jerry Jex et al. U.S. Pat. No. 5,598,113 describes a mixed-clock FIFO circuit. However, the FIFO circuit described in '113 has a significantly greater area overhead in implementing the synchronization. For example, this design has two synchronizers for every cell.
Accordingly, there exists a need in the art for a FIFO circuit having low latency and high throughput and capable of operation in mixed synchronous/asynchronous environments.